This invention relates to a semiconductor memory device and especially to an output circuit of a MOS dynamic memory device in which the output level is sufficiently increased.
As shown in FIG. 1, a MOS dynamic memory device generally comprises a sense amplifier circuit SA and a group of column decoders 10 arranged in the center of a semiconductor substrate (chip), as well as a group of memory cells 11; 12 and a group of row decoders 13; 14 arranged on both sides of the semiconductor substrate. In the memory device, a sense buffer circuit 15 is connected to a pair of data buses DB and DB leading from the group of column decoders 10, and a data output D.sub.out is obtained by a system consisting of a sense buffer circuit 15, an output buffer circuit 16, and a group of output transistors 17. In FIG. 1, CL.sub.1 through CL.sub.n indicate output signals of the column decoders 10; Q.sub.1 through Q.sub.n2 indicate gate transistors which are turned on and off by the output signals CL.sub.1 through CL.sub.n ; BL.sub.1 through BL.sub.n indicate bit lines; and 18 and 19 indicate, respectively, an SBE (sense buffer enable) signal generator and on OBE (output buffer enable) signal generator, the SBE and OBE signals actuating, respectively, the sense buffer circuit 15 and the output buffer circuit 16.
The OBE generator 19, the output buffer circuit 16, and the group of output transistors 17 of the device of FIG. 1 are illustrated in detail in FIG. 2. As shown in FIG. 2, the OBE generator 19 consists of MOS transistors Q.sub.11 through Q.sub.22, the output buffer circuit 16 consists of MOS transistors Q.sub.31 through Q.sub.34, and the group of output transistors 17 consists of MOS transistors Q.sub.41 and Q.sub.42. The transistors Q.sub.11 through Q.sub.22, Q.sub.31 through Q.sub.34, and Q.sub.41 and Q.sub.42 are connected between the voltage sources V.sub.CC and V.sub.SS. In FIG. 2, N1 through N5 and N11 and N12 indicate nodes, and RST indicates a reset signal.
The operation of the circuit in FIG. 2 will be described with reference to FIG. 3, in which various waveforms of the voltages of signals appearing in the circuit are illustrated.
At first, when the SBE signal from the signal generator 18 rises up, the sense buffer circuit 15 is actuated and starts to operate to turn one of the outputs RD and RD to the "H" level and the other output to the "L" level in accordance with the read-out data from the data buses DB and DB. In the case of FIG. 3, it turns the output RD to the "H" level and the output RD to the "L" level. The output buffer circuit 16 receives the signals OBE, RD, and RD, and in the circuit 16, according to the signal RD, the transistor Q.sub.34 is turned ON and the transistor Q.sub.33 is turned OFF. Therefore, one output OUT rises up in accordance with the rising up of the signal OBE and the other output OUT remains at the "L" level.
In the group of output transistors 17 receiving the output signals OUT and OUT, the transistor Q.sub.41 is turned ON, the transistor Q.sub.42 is turned OFF, and, accordingly, the output signal D.sub.out is turned to the "H" level.
In the above-mentioned memory device, the "H" level of the output signal OBE from the signal generator is almost equal to the level of the voltage source V.sub.CC due to the bootstrap effect produced by the MOS capacitor Q.sub.19. Accordingly, even though this "H" level of the output signal OBE may be transmitted directly to the output signal OUT or OUT of the output buffer circuit 16 by means of the bootstrap effect of the gate capacitance of the transistor Q.sub.33 or Q.sub.34, the maximum level of the signals OUT, OUT is that of the voltage source V.sub.CC. Therefore the level of the final output signal D.sub.out becomes less than the voltage source V.sub.CC, at least by the threshold level V.sub.TH of the transistor Q.sub.41. Though it is necessary that the "H" level V.sub.OH of the final output D.sub.out be higher than 2.4 V under the condition that the load current of the predetermined value is flowing, it may be difficult to fulfill the above-mentioned requirement in any case in accordance with the circuit of FIG. 2. For example, assuming that the voltage source is V.sub.CC =4.5 V and the threshold level of the transistor Q.sub.41 is V.sub.TH =1.0, the maximum level of the output D.sub.out is less than (V.sub.CC -V.sub.TH)=3.5 V, and when the load current increases the level of the output D.sub.out decreases to less than 3.5 V so that it may be less than 2.4 V. In such a situation, the rising up of the output D.sub.out is slow, as shown in FIG. 3, and, accordingly, the access time of the memory device increases.